Ethernet has undergone amazing changes since the concept was originally documented in 1973. The IEEE 802.3™ “Standard for Ethernet” initially was developed in order to standardize connectivity among personal computers, printers, servers and other devices inside a local area network (LAN), but the standard has steadily evolved to deliver increased capacities and connect more devices, users, media types and protocols across more types of networks. In only the last five years, the pace of change has accelerated substantially. The proliferation of smart phones, tablets, Wi- Fi, 3G/4G/LTE mobile deployments, 10 Gb/s servers, Internet-enabled TV, the cloud and its associated applications, social media, video calling, online gaming and new database technologies has ratcheted up the bandwidth pressure on the Ethernet interconnect space. Though data centers—the eye of the bandwidth storm—for years relied on 1 Gb/s server interconnections, the industry appears poised to rapidly leapfrog through the standardized 10 Gb/s, 40 Gb/s and 100 Gb/s Ethernet speed steps.
Now I would like to discuss about 100 –Gb/s and beyond SMF (Single Mode Fiber) Ethernet (datacom) optical interfaces based on WDM technology.FIRST GENERATION 100-GB/S SMF ETHERNET
First Generation (Gen1) 100-Gb/s Ethernet transceivers use discrete optical components based on existing technologies, driven by demand for quick time to market delivery of interoperable modules from multiple optics suppliers.A. Architecture
Figure 1 shows the architecture of a Gen1 100-Gb/s Ethernet transceiver. It supports reaches up to 10 km and is referred to as 100GBASE-LR4. Also shown is the 40km architecture, referred to as 100GBASE-ER4. Both optical interfaces are specified by the IEEE.
Fig. 1. 100Gb/s Gen1 10km and 40km WDM Transceiver.
The lane rate of the electrical interface is 10-Gb/s, determined by I/O rates in mainstream CMOS technologies used for the MAC (media access controller) IC, which connects to the 100-Gb/s optical transceiver.B. Optical Wavelengths
The optical lane rate is 25-Gb/s and uses low cost NRZ modulation. The four lanes are wavelength division multiplexed (WDM) over a single fiber in each transmission direction. The exact optical lane grid is referred to as LAN WDM, and is listed in Table I.
Table I C. Components
Translation between the 10-Gb/s and 25-Gb/s lane rates uses 10:4 SerDes (serializer de-serializer) ICs. The transmitter uses four MDs (modulator drivers) and four discrete cooled EMLs (electro-absorption modulator lasers) connected with fiber to WDM Mux (multiplexer) which combines the four wavelengths. The receiver uses WDM DeMux (de-multiplexer), four PINs (p-intrinsic-n) photodiodes, and four TIAs (trans-impedance amplifiers). A LA (limiting amplifier) function is either in the TIAs or SerDes ICs. For 40km distances, a SOA (semiconductor optical amplifier) is added.D. Module
The transceiver is packaged in the CFP (100-Gb/s Form-factor Pluggable) module, as specified by the CFP MSA. To minimize cost, surface-mount components and PCB (printed circuit board) transmission-line RF interconnect is used.E. Deployment
100-Gb/s CFP modules have been reported by multiple optics suppliers like Verizon, Opnext etc. Verizon introduces the first Coherent 100G DWDM trials in 2010.SECOND GENERATION 100-GB/S SMF ETHERNET
Second generation (Gen2) 100-Gb/s Ethernet transceivers will be driven by long term high volume requirements for low cost, small size and reduced power.A. Architecture
Figure 2 shows architecture of a Gen2 100-Gb/s Ethernet transceiver. The optical interface is fully interoperable with Gen1 transceivers.
Fig. 2. 100Gb/s Gen2 10km WDM Transceiver.
The electrical lane rate is 25-Gb/s, which reduces the interface width and simplifies the ICs. The 4x25-Gb/s I/O specification is being defined in the OIF (Optical Interface Forum) CEI (Common Electrical Interface) 28G-VSR project. Initially, the transceiver will be connected to MAC IC through 10:4 SerDes ICs, but long term will migrate to direct 25-Gb/s MAC IC connection.B. Components
The 25-Gb/s electrical interface requires quad CDR (Clock and Data Recovery) IC. The transmitter uses quad LD (laser driver) and quad cooled DML (directly modulated laser.) The connection to the WDM Mux is on a photonic circuit. The receiver WDM DeMux connection to the quad PIN is also on a photonic circuit.C. Photonic Integrated Technology
The enabling technology for Gen2 transceivers is photonic integration. Feasible approaches are Hybrid Planar Lightguide Circuit (PLC), and monolithic InP Photonic Integrated Circuit (PIC).D. Module
The transceiver will be packaged in the CFP2 module, now under definition by the CFP MSA. The module will be about half the width of the CFP to double port density.References:
1. 100-Gb/s and Beyond Ethernet Optical Interfaces
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